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[ARM-PowerPC-ColdFire-MIPS] RISC_Core.ZIP

Description: 这是一篇关于8位RISC CPU设计的文章，其中包含了用Verilog语言编写的CPU内核程序-This is an 8-bit RISC CPU on the design of the article, which includes using the Verilog language CPU core procedures
Platform: | Size: 340992 | Author: jinzhoulang | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 用verilog编写的32位alu部件，用于cpu制作-Prepared using Verilog 32 alu parts, used cpu production
Platform: | Size: 3072 | Author: 胡豫陇 | Hits:

[VHDL-FPGA-Verilog] elock.verilog.pdf

Description: 一种基于Verilog的电子密码锁的论文介绍。有部分程序代码。-Verilog-based electronic locks thesis introduction. Some program code.
Platform: | Size: 294912 | Author: 李里 | Hits:

[VHDL-FPGA-Verilog] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Platform: | Size: 219136 | Author: hulin | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] simu_NIOS

Description: 和NIOS功能一样的CPU，可以在FPGA上运行,Verilog源代码-NIOS function and the same CPU, the FPGA can run, Verilog source code
Platform: | Size: 53248 | Author: zx | Hits:

[Windows Develop] simplecpu

Description: 一个16位简单CPU的Verilog源代码。-A CPU of 16 simple Verilog source code.
Platform: | Size: 79872 | Author: qiuyuwu | Hits:

[Windows Develop] CPU_interface_verilog_code

Description: 包括一个基本的CPU接口的verilog程序及激励程序。-Including a basic Verilog CPU interface procedures and incentive program.
Platform: | Size: 1024 | Author: 幻婳 | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[Other] RiscCpu

Description: Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Platform: | Size: 9216 | Author: sss | Hits:

[VHDL-FPGA-Verilog] TINY3

Description: verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
Platform: | Size: 1660928 | Author: songbo | Hits:

[OS program] 8086IP

Description: 开源CPU软核8086的源码,波兰版Verilog源码-8086 soft-core CPU revenue source, the Polish version of Verilog source code
Platform: | Size: 71680 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] RISC8.ZIP

Description: verilog RISC8 cpu CORE 8位RISC CPU 内核源码（VERILOG 版）-verilogRISC8 cpu CORE8-bit RISC CPU core source (VERILOG version)
Platform: | Size: 80896 | Author: likui | Hits:

[VHDL-FPGA-Verilog] mipsCPU

Description: MIPS CPU tested in Icarus Verilog
Platform: | Size: 20480 | Author: imromeo | Hits:

[Windows Develop] RISC_8

Description: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Platform: | Size: 173056 | Author: WangYong | Hits:

[VHDL-FPGA-Verilog] KD_CPU_src

Description: verilog语言写的8位CPU源代码，基本的算术运算和逻辑运算，对于学习计算机原理和verilog语言都有良好的效果-Verilog Language Writing 8-bit CPU source code, the basic arithmetic operations and logic operations, the study of computer principles and Verilog language has good results
Platform: | Size: 57344 | Author: zz | Hits:

[VHDL-FPGA-Verilog] Microprocessor

Description: 精通verilog HDL语言编程的一个不错的cpu 代码-Verilog HDL language proficiency of a good cpu code
Platform: | Size: 774144 | Author: 孟霑 | Hits:

[assembly language] 111.ver

Description: verilog code for CPU design by Mohammad Hosseini.
Platform: | Size: 2048 | Author: Mohammad | Hits:

[Windows Develop] CPU_verilog

Description: 一个4级流水线CPU的verilog代码，供参考学习使用，有些语句不能综合，可以通过它学习CPU的工作原理。-A 4-stage pipeline CPU' s verilog code, learning to use for reference, some statements can not be integrated, you can learn from CPU through its works.
Platform: | Size: 63488 | Author: xq | Hits:

[VHDL-FPGA-Verilog] 8bit_RISC_CPU_RTL_Code

Description: 8位RISC CPU 内核源码(VERILOG版)-8 bit RSIC CPU RTL code(Verilog)
Platform: | Size: 79872 | Author: 曾亮 | Hits:
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